Automatic test equipment provides semiconductor manufacturers the capability of individually testing each and every semiconductor device fabricated during production. The testing is usually carried out at both the wafer level and the packaged-device level to ensure operability of the devices before reaching the marketplace.
Modern semiconductor devices typically have anywhere from thirty-two to over one-thousand pins, generally requiring a corresponding number of channels in the semiconductor tester to thoroughly verify the operation of the device. Each channel usually comprises a signal path including the necessary pin electronics for sending and/or receiving test signals to and from a pin on the DUT. In conventional testers, to maximize component density and minimize the size of the tester, the channels are often formed on printed circuit boards resident within a testhead. The testhead is separated from the main body of the tester for coupling to the DUTs that are mounted on a prober or handler.
Because of the relatively high concentration of circuit boards within a conventional testhead, specialized cooling systems are generally employed to maintain a stable thermal environment. One proposal for such a cooling system is found in U.S. Pat. No. 5,889,651 to Sasaki et al. This patent discloses a cooling system for a conventional testhead type of tester and employs an annular air duct disposed within a testhead housing. The duct abuts a plurality of radially disposed circuit boards and includes airways that project radially inwardly between adjacent boards. Each airway is formed with nozzles that direct air perpendicular to the boards to effect cooling.
While this proposal would appear to work well for its intended applications, the elaborate ducting takes up valuable space within the testhead, contributing to a larger overall footprint for the tester. Moreover, because of the direct impingement of the airflow perpendicular to the boards, the capacity of the cooling fans would appear to be relatively large in order to overcome the resistive effects of the ducting and the nozzles. Consequently, from a material and operating cost perspective, the Sasaki proposal appears to have several undesirable drawbacks.
In an effort to overcome the direct-impingement drawback, two similar proposals disclosed in U.S. Pat. Nos. 5,644,248 and 5,767,690 to Fujimoto employ a linear airflow construction. Like the Sasaki disclosure, the Fujimoto systems are employed in a conventional testhead and include an air duct disposed inside the testhead housing. A plurality of fans and heat exchangers are used to circulate air between parallel arrays of circuit boards in a horizontal circular path.
Although the Fujimoto proposals also appear beneficial for their intended purposes, they suffer from many of the drawbacks associated with the Sasaki system. This includes the additional air duct that displaces valuable circuit board space, and the implementation of a horizontal air path. Due to the horizontal nature of the airflow path, multiple fans and heat exchangers appear to be required to ensure adequate airflow across the circuit boards. The additional fans and heat exchangers undesirably adds both complexity and cost to the system.
While the cooling systems described above exemplify the art for conventional testhead-type semiconductor testers, modern tester designs have begun employing integrated test cells that eliminate the separateness of the conventional testhead from the body of the tester. The test system takes advantage of the vertical space in a semiconductor manufacturers' clean room, dramatically improving the tester footprint. In effect, the circuit boards that couple to the DUT do so from within the tester, and are supported by the tester frame. Such a configuration is described in copending U.S. patent application Ser. No. 09/410,857, entitled "Integrated Test Cell", filed Oct. 1, 1999, assigned to the assignee of the present invention and expressly incorporated herein by reference.
What is needed and heretofore unavailable is a cooling system that minimizes costly components and correspondingly reduces operating costs to sufficiently cool arrays of circuit board assemblies in a semiconductor tester. Moreover, the need exists for such a cooling system that takes advantage of the vertical nature of an integrated test cell.